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A CAD suite for high-performance FPGA design
Type Conference Paper Author B. Hutchings Author P. Bellows Author J. Hawkins Author S. Hemmert Author B. Nelson Author M. Rytting Date 1999 Proceedings Title Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375) Conference Name Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines Place Napa Valley, CA, USA Pages 12-24 DOI 10.1109/FPGA.1999.803663 URL http://www.computer.org/portal/web/csdl/doi?
doc=doi/10.1109/FPGA.1999.803663Accessed Saturday, September 25, 2010 2:45:11 PM Library Catalog CrossRef Date Added Saturday, September 25, 2010 2:45:11 PM Modified Saturday, September 25, 2010 3:00:47 PM Attachments
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A Comparison of TMR With Alternative Fault-Tolerant Design Techniques for FPGAs
Type Journal Article Author K.S. Morgan Author D.L. McMurtrey Author B.H. Pratt Author M.J. Wirthlin Abstract With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR. Publication Nuclear Science, IEEE Transactions on Volume 54 Issue 6 Pages 2065-2072 Date 2007 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2007.910871 ISSN 0018-9499 URL 10.1109/TNS.2007.910871 Accessed Saturday, September 25, 2010 3:15:13 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:15:13 PM Modified Saturday, September 25, 2010 3:15:13 PM Tags:
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A Comparison Study on Implementing Optical Flow and Digital Communications on FPGAs and GPUs
Type Journal Article Author John Bodily Author Brent Nelson Author Zhaoyi Wei Author Dah-Jye Lee Author Jeff Chase Abstract FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing computations. Applications successfully implemented on FPGAs typically contain high levels of parallelism and often use simple statically scheduled control and modest arithmetic. Recently introduced computing devices such as coarse-grain reconfigurable arrays, multi-core processors, and graphical processing units promise to significantly change the computational landscape and take advantage of many of the same application characteristics that fit well on FPGAs. One real-time computing task, optical flow, is difficult to apply in robotic vision applications because of its high computational and data rate requirements, and so is a good candidate for implementation on FPGAs and other custom computing architectures. This article reports on a series of experiments mapping a collection of different algorithms onto both an FPGA and a GPU. For two different optical flow algorithms the GPU had better performance, while for a set of digital comm MIMO computations, they had similar performance. In all cases the FPGA implementations required 10x the development time. Finally, a discussion of the two technology’s characteristics is given to show they achieve high performance in different ways. Publication ACM Trans. Reconfigurable Technol. Syst. Volume 3 Issue 2 Pages 1-22 Date 2010 DOI 10.1145/1754386.1754387 URL http://portal.acm.org/citation.cfm?
id=1754387Accessed Saturday, September 25, 2010 3:19:18 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:19:18 PM Modified Saturday, September 25, 2010 3:19:18 PM Tags:
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A description, analysis, and comparison of a hardware and a software implementation of the SPLASH genetic algorithm for optimizing symmetric traveling salesman problems
Type Journal Article Author Paul S Graham Date 1996 URL http://citeseerx.ist.psu.edu/viewdoc/summary?
doi=10.1.1.126.5470Accessed Saturday, September 25, 2010 3:00:00 PM Date Added Saturday, September 25, 2010 3:00:00 PM Modified Saturday, September 25, 2010 3:00:00 PM -
A dynamic instruction set computer
Type Conference Paper Author M.J. Wirthlin Author B.L. Hutchings Abstract A dynamic instruction set computer (DISC) has been developed that supports demand-driven modification of its instruction set. Implemented with partially reconfigurable FPGAs, DISC treats instructions as removable modules paged in and out through partial reconfiguration as demanded by the executing program. Instructions occupy FPGA resources only when needed and FPGA resources can be reused to implement an arbitrary number of performance-enhancing application-specific instructions. DISC further enhances the functional density of FPGAs by physically relocating instruction modules to available FPGA space Date 1995 Proceedings Title FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on Conference Name FPGAs for Custom Computing Machines, 1995. Proceedings. IEEE Symposium on Pages 99-107 DOI 10.1109/FPGA.1995.477415 URL 10.1109/FPGA.1995.477415 Accessed Saturday, September 25, 2010 4:00:37 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 4:00:37 PM Modified Saturday, September 25, 2010 4:00:37 PM Tags:
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A Fast and Accurate Tensor-based Optical Flow Algorithm Implemented in FPGA
Type Conference Paper Author Zhaoyi Wei Author Dah-Jye Lee Author Dah-Jye Lee Author Brent Nelson Author Michael Martineau Abstract Many computer vision applications require realtime processing of image data. This requirement is especially critical for autonomous vehicles performing obstacle avoidance, path planning, and target tracking tasks. A quickly calculated and relatively rough motion estimate is more useful for autonomous navigation than a more accurate, but slowly calculated estimate. Recent technology advancements in small unmanned air and ground vehicles make many low-cost surveillance and military applications possible. Most of these applications demand a low power, compact, light weight, and high speed computation platform for processing image data in real time. In most cases, the traditional general purpose processor and sequentially executed software approach does not meet these requirements. In this paper, a tensorbased optical flow algorithm is modified and implemented using field programmable gate array (FPGA) for small unmanned vehicle obstacle avoidance and navigation. Date 2007 Proceedings Title Applications of Computer Vision, IEEE Workshop on Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 18 DOI http://doi.ieeecomputersociety.org/10.1109/WACV.2007.5 Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 3:22:17 PM Modified Saturday, September 25, 2010 3:22:17 PM Notes:
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A flexible circuit switched NOC for FPGA based systems
Type Conference Paper Author C. Hilton Author B. Nelson Abstract Increases in chip density due to Moore's Law allow for the implementation of ever larger and more complex systems on a single chip. The communication mechanisms employed in such SOC's is an important contribution to their overall performance. Networks on chip promise to overcome the scalability problems found in bus-based interconnect. Most work to this point has focused on packet-switched NOC's. Circuit-switched networks are a lightweight alternative that promise high communication rates and predictable communication latencies. This paper describes PNoC, a very flexible circuit-switched NOC suitable for use in FPGA-based systems. Implementation results on a Virtex-il Pro device are given using an image binarization demonstration which resulted in a 2 - 23x speedup with a 29% area overhead compared to a shared bus implementation. Date 2005 Proceedings Title International Conference on Field Programmable Logic and Applications Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 191-196 DOI http://doi.ieeecomputersociety.org/10.1109/FPL.2005.1515721 ISBN 0-7803-9362-7 Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 3:25:18 PM Modified Saturday, September 25, 2010 3:25:18 PM Tags:
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A Hardware Genetic Algorithm for the Travelling Salesman Problem on SPLASH 2
Type Conference Paper Author Paul Graham Author Brent E. Nelson Date 1995 Proceedings Title Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 352-361 ISBN 3-540-60294-1 URL http://portal.acm.org/citation.cfm?
id=647922.760933Accessed Saturday, September 25, 2010 3:41:47 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:41:47 PM Modified Saturday, September 25, 2010 3:41:47 PM Attachments
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A Low-Variance and Low-Complexity Carrier-Frequency-Offset Estimator using Multiple Pilot Sequences
Type Conference Paper Author Joseph M. Palmer Author Michael Rice Author Brent Nelson Abstract A data-aided carrier frequency offset estimator is proposed. The proposed estimator is novel because it operates on multiple pilot sequences, spaced in time. Various papers have been presented which prove the estimation performance advantages of using such a scheme. However, little work has been presented on practical estimators which achieve these improved bounds. The new estimator is based on the family of phase-increment frequency estimator methods. Hence, it is low-complexity, as well as highly accurate. Date 2007 Proceedings Title Military Communications Conference, 2007. MILCOM 2007. IEEE Conference Name Military Communications Conference, 2007. MILCOM 2007. IEEE Pages 1-7 DOI 10.1109/MILCOM.2007.4454903 URL 10.1109/MILCOM.2007.4454903 Accessed Saturday, September 25, 2010 3:22:52 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:22:52 PM Modified Saturday, September 25, 2010 3:22:52 PM -
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Type Conference Paper Author A. Arnesen Author N. Rollins Author M. Wirthlin Abstract Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and verified intellectual property (IP) cores. This paper presents CHREC XML, a XML schema that facilitates IP reuse by encapsulating the details of reusable IP cores at multiple levels of abstraction. This schema is independent from any design language or tool and can be used by any tool to understand many details about the interface of a reusable circuit. An IP integration tool was also created based on this schema to demonstrate the ease of IP reuse when cores are described in this meta-data description. This IP integration tool allows a designer to easily select and integrate IP cores from a variety of languages/tools and automatically run the appropriate tools to generate the cores in a form usable by downstream implementation tools. Date 2009 Proceedings Title Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Conference Name Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Pages 472-475 DOI 10.1109/FPL.2009.5272468 ISBN 1946-1488 URL 10.1109/FPL.2009.5272468 Accessed Saturday, September 25, 2010 3:51:59 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:51:59 PM Modified Saturday, September 25, 2010 3:51:59 PM Tags:
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A Parallel FFT Architecture for FPGAs
Type Conference Paper Author Joseph Palmer Author Brent Nelson Date August 2004 Conference Name In Proceedings of the 14th International Conference on Field Programmable Logic and Applications (FPL'2004) Pages 948-953 URL http://www.springerlink.com/content/pydy7nk9vt750q90/ Accessed Saturday, September 25, 2010 3:28:07 PM Date Added Saturday, September 25, 2010 3:28:07 PM Modified Saturday, September 25, 2010 3:30:55 PM Attachments
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A reconfigurable computing architecture for microsensors
Type Conference Paper Author S. Scalera Author M. Falco Author B. Nelson Date April 2000 Proceedings Title Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871) Conference Name 2000 IEEE Symposium on Field-Programmable Custom Computing Machines Place Napa Valley, CA, USA Pages 59-67 DOI 10.1109/FPGA.2000.903393 URL http://www.computer.org/portal/web/csdl/doi?
doc=doi/10.1109/FPGA.2000.903393Accessed Saturday, September 25, 2010 3:36:03 PM Library Catalog CrossRef Date Added Saturday, September 25, 2010 3:36:03 PM Modified Saturday, September 25, 2010 3:36:20 PM Attachments
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A test methodology for determining space-readiness of Xilinx SRAM-based FPGA designs
Type Conference Paper Author H. Quinn Author P. Graham Author K. Morgan Author M. Caffrey Author J. Krone Abstract Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an very active area of research for the past decade. Since both the circuit and the circuitpsilas state are stored in radiation-tolerant memory, both could be altered by the harsh space radiation environment. Both the circuit and the circuitpsilas state can be protected by triple-modular redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and modeling. While accelerator testing is the current ldquogold standardrdquo for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors earlier in the design process. Date 2008 Proceedings Title AUTOTESTCON, 2008 IEEE Conference Name AUTOTESTCON, 2008 IEEE Pages 252-258 DOI 10.1109/AUTEST.2008.4662621 ISBN 1088-7725 URL 10.1109/AUTEST.2008.4662621 Accessed Saturday, September 25, 2010 3:44:09 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:44:09 PM Modified Saturday, September 25, 2010 3:44:09 PM Tags:
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Accelerator validation of an FPGA SEU simulator
Type Journal Article Author E. Johnson Author M. Caffrey Author P. Graham Author N. Rollins Author M. Wirthlin Abstract An accelerator test was used to validate the performance of an FPGA single event upset (SEU) simulator. The Crocker Nuclear Laboratory cyclotron proton accelerator was used to irradiate the SLAAC1-V, a Xilinx Virtex FPGA board. We also used the SLAAC1-V as the platform for a configuration bitstream SEU simulator. The simulator was used to probe the "sensitive bits" in various logic designs. The objective of the accelerator experiment was to characterize the simulator's ability to predict the behavior of a test design in the proton beam during a dynamic test. The test utilized protons at 63.3 MeV, well above the saturation cross-section for the Virtex part. Protons were chosen because, due to their lower interaction rate, we can achieve the desired upset rate of about one configuration bitstream upset per second. The design output errors and configuration upsets were recorded during the experiment and compared to results from the simulator. In summary, for an extensively tested design, the simulator predicted 97% of the output errors observed during radiation testing. The SEU simulator can now be used with confidence to quickly and affordably examine logic designs to 'map' sensitive bits, to provide assurance that incorporated mitigation techniques perform correctly, and to evaluate the costs and benefits of various mitigation strategies. The simulator provides an excellent test environment that accurately represents radiation induced configuration bitstream upsets. Publication Nuclear Science, IEEE Transactions on Volume 50 Issue 6 Pages 2147-2157 Date 2003 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2003.821791 ISSN 0018-9499 URL 10.1109/TNS.2003.821791 Accessed Saturday, September 25, 2010 3:47:00 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:47:00 PM Modified Saturday, September 25, 2010 3:47:00 PM Tags:
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An Assessment Of The Suitability Of Reconfigurable Systems For Digital Signal Processing
Type Journal Article Author Russell J Petersen Author Brad L Hutchings Author D. Jeffs Author Wynn C Stirling Date 1995 URL http://citeseerx.ist.psu.edu/viewdoc/summary?
doi=10.1.1.48.1420Accessed Saturday, September 25, 2010 3:05:13 PM Date Added Saturday, September 25, 2010 3:05:13 PM Modified Saturday, September 25, 2010 3:05:13 PM -
An FPGA-based Space-time Coded Telemetry Receiver
Type Conference Paper Author C. Lavin Author B. Nelson Author J. Palmer Author M. Rice Abstract The significant problem of data dropouts in aeronautical telemetry due to multiple transmit antennas has escalated as transmit data rates have increased. A proposed solution of using a space-time coded signal can resolve these data dropouts at the expense of increased receiver complexity. This paper describes an implementation overview of an FPGA-based space-time coded telemetry receiver and the various challenges associated with its realization. In addition, we discuss the productivity of the high-level design tool used in constructing the receiver, Xilinx system generator for DSP. With some overhead in terms of FPGA fabric usage and clock speed, our estimates show a 2 - 3x productivity improvement over standard HDLs. Date 2008 Proceedings Title Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National Conference Name Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National Pages 250-256 DOI 10.1109/NAECON.2008.4806555 ISBN 7964-0977 URL 10.1109/NAECON.2008.4806555 Accessed Saturday, September 25, 2010 3:13:54 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:13:54 PM Modified Saturday, September 25, 2010 3:50:55 PM Tags:
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An XML Schema for Representing Reusable IP Cores for Reconfigurable Computing
Type Conference Paper Author N. Rollins Author A. Arnesen Author M. Wirthlin Abstract The reuse of intellectual property (IP) cores within reconfigurable computing systems is a promising approach for improving the productivity of reconfigurable system design. Further, there are a large variety of reusable IP cores available for a variety of application-specific functions. These cores, however, are created from different design tools and are difficult to integrate into a single reconfigurable system design. To facilitate the reuse of these cores, an XML schema has been created for representing the essential details of a core in a reconfigurable computing design environment. This paper presents this XML schema and describes how it can be used to facilitate reuse in reconfigurable computing systems. Date 2008 Proceedings Title Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National Conference Name Aerospace and Electronics Conference, 2008. NAECON 2008. IEEE National Pages 190-197 DOI 10.1109/NAECON.2008.4806545 ISBN 7964-0977 URL 10.1109/NAECON.2008.4806545 Accessed Saturday, September 25, 2010 4:01:31 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 4:01:31 PM Modified Saturday, September 25, 2010 4:01:31 PM Tags:
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Bitstream compression through frame removal and partial reconfiguration
Type Conference Paper Author B. Sellers Author J. Heiner Author M. Wirthlin Author J. Kalb Abstract As FPGA logic density continues to increase, new techniques are needed to store initial configuration data efficiently, maintain usability, and minimize cost. In this paper, a novel compression technique is presented for Xilinx Virtex partially reconfigurable FPGAs. This technique relies on constrained hardware design and layout combined with a few simple compression techniques. This technique uses partial reconfiguration to separate a hardware design into two separate regions: a static and partial region. A bitstream containing only the static region is then compressed by removing empty frames. This bitstream will be stored in non-volatile memory and used for initialization. The remaining logic is configured through partial reconfiguration over a communication network. By applying this technique, a high level of compression was achieved (almost 90% for the V4 LX25). This compression technique requires no extra decompression circuitry and compression levels improve as device size increases. Date 2009 Proceedings Title Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Conference Name Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Pages 476-480 DOI 10.1109/FPL.2009.5272502 ISBN 1946-1488 URL 10.1109/FPL.2009.5272502 Accessed Saturday, September 25, 2010 3:51:36 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:51:36 PM Modified Saturday, September 25, 2010 3:51:36 PM Tags:
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Comparing fine-grained performance on the Ambric MPPA against an FPGA
Type Conference Paper Author B. Hutchings Author B. Nelson Author S. West Author R. Curtis Abstract A simple image-processing application is implemented on the Ambric MPPA and an FPGA, using a similar implementation for both devices. FPGAs perform extremely well on this kind of application and provide a good benchmark for comparison. The Ambric implementation starts out with a naive implementation and proceeds through several design optimizations until it reaches a maximum frame rate of 164 FPS (512 times 512 images) which turns out to be approximately 7times slower than the FPGA. The final Ambric implementation uses only 18 of 336 available processors, achieves more than sufficient performance for realtime embedded applications, and has excess processors to use for implementing additional algorithms. After introducing the image processing application and its implementation on both devices, the paper compares and contrasts the intrinsic, general characteristics of Ambric MPPA and FPGA devices. Date 2009 Proceedings Title Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Conference Name Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Pages 174-179 DOI 10.1109/FPL.2009.5272505 ISBN 1946-1488 URL 10.1109/FPL.2009.5272505 Accessed Saturday, September 25, 2010 3:06:23 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:06:23 PM Modified Saturday, September 25, 2010 3:06:23 PM Tags:
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Configurable computing and sonar processing - architectures and implementations
Type Conference Paper Author B.E. Nelson Abstract Sonar beamforming is an ideal application for reconfigurable computing due to its high available levels of parallelism, relatively low sample rates and modest word sizes. We describe a family of beamforming algorithms and their implementation using configurable computing technology. These include algorithms for time-delay, frequency-domain and matched field beamforming. Configurable computing architectures appropriate for each are described and the tradeoffs associated with the mapping of each to concrete platforms is discussed Date 2001 Proceedings Title Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on Conference Name Signals, Systems and Computers, 2001. Conference Record of the Thirty-Fifth Asilomar Conference on Volume 1 Pages 56-60 vol.1 DOI 10.1109/ACSSC.2001.986880 URL 10.1109/ACSSC.2001.986880 Accessed Saturday, September 25, 2010 3:34:16 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:34:16 PM Modified Saturday, September 25, 2010 3:34:16 PM Tags:
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Constant Coefficient Multiplication Using Look-Up Tables
Type Journal Article Author Michael J. Wirthlin Abstract Multiplication is an important but expensive operation in most FPGA-based signal processing systems. Many techniques have been introduced for reducing the size and improving the speed of FPGA-based multipliers. Constant-coefficient multipliers are an important class of such multipliers that reduce FPGA resource requirements by exploiting constant-specific optimizations. This paper reviews and analyzes a constant coefficient multiplier that exploits the fine-grain memory resources of FPGAs by performing table look-up. Several optimizations to this multiplier are introduced and analyzed. This paper will also introduce several techniques for reducing the resources of this multiplier by exploiting modern FPGA architectural enhancements. Publication J. VLSI Signal Process. Syst. Volume 36 Issue 1 Pages 7-15 Date 2004 URL http://portal.acm.org/citation.cfm?
id=960089.960093Accessed Saturday, September 25, 2010 3:47:43 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:47:43 PM Modified Saturday, September 25, 2010 3:47:43 PM Tags:
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Debug methods for hybrid CPU/FPGA systems
Type Conference Paper Author E. Roesler Author B. Nelson Abstract The combining of one or more CPU's and an FPGA fabric on the same die is growing in popularity. Such programmable system-on-chip (PSOC) systems promise performance and development time advantages over conventional technology. In a PSOC design, design errors may occur in many different places - the design of the CPU, the embedded software, the FPGA-based parts of the design, or the interfaces between these various parts. This paper presents a flexible tool that allows the user to dynamically adapt the CAD tool's behavior to the level of detail needed to track down design errors in PSOC designs. It provides for the creation of and coexistence of software source debuggers and gate level debug tools, all incorporated into the same debugging environment. A prototype PSOC debugging system based on a derivative of the JHDL CAD tool is presented which illustrates the range of debug support in both simulation and hardware execution modes that can be provided for PSOC debug. Extensions to the tool to support a wider range of embedded processors and GNU compiler tools are discussed along with conclusions and future work. Date 2002 Proceedings Title Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on Conference Name Field-Programmable Technology, 2002. (FPT). Proceedings. 2002 IEEE International Conference on Pages 243-250 DOI 10.1109/FPT.2002.1188688 URL 10.1109/FPT.2002.1188688 Accessed Saturday, September 25, 2010 2:57:12 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 2:57:12 PM Modified Saturday, September 25, 2010 2:57:12 PM Tags:
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Design, Debug, Deploy: The Creation of Configurable Computing Applications
Type Journal Article Author Brent E. Nelson Author Brad L. Hutchings Author Michael J. Wirthlin Publication Journal of Signal Processing Systems Volume 53 Issue 1-2 Pages 187-196 Date 4/2008 Journal Abbr J Sign Process Syst Sign Image Video Technol DOI 10.1007/s11265-008-0167-9 ISSN 1939-8018 Short Title Design, Debug, Deploy URL http://www.springerlink.com/content/9087034917m04ll7/ Accessed Saturday, September 25, 2010 3:06:37 PM Library Catalog CrossRef Date Added Saturday, September 25, 2010 3:06:37 PM Modified Saturday, September 25, 2010 3:06:37 PM Attachments
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Designing and Debugging Custom Computing Applications
Type Journal Article Author Brad Hutchings Author Brent Nelson Author Michael J. Wirthlin Abstract Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references. Publication IEEE Des. Test Volume 17 Issue 1 Pages 20-28 Date 2000 URL http://portal.acm.org/citation.cfm?
id=622197.622950Accessed Saturday, September 25, 2010 2:48:57 PM Library Catalog ACM Date Added Saturday, September 25, 2010 2:48:57 PM Modified Saturday, September 25, 2010 2:48:57 PM Attachments
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Developing and debugging FPGA applications in hardware with JHDL
Type Conference Paper Author B. Hutchings Author B. Nelson Abstract JHDL is a Java-based suite of design tools developed at Brigham Young University to aid in the design and development of high-performance FPGA applications. The suite consists of a set of JHDL circuit libraries, simulator, schematic generator, hardware debugger and other tools that can be used to design, develop and debug designs. JHDL is a unique design tool that unifies simulation and hardware execution into a single environment. Designers can easily select either simulation or execution and all of the circuit verification and visualization tools are fully usable whether in simulation or hardware execution mode. Because of its unified simulation/execution design environment, JHDL is the first tool that directly supports symbolic debugging of a user design in the original design context while the design is actually executing in FPGA hardware. JHDL allows designers to exploit the immediate availability of FPGA hardware making it possible to test and symbolically debug designs at hardware speeds that run several orders of magnitude faster than simulation. JHDL also supports end-to-end application development of the user circuitry including any control code and any user interface software including graphical user interfaces (GUIs). User circuitry is designed using JHDL libraries while control software and user interface software is written using standard Java libraries such as Swing, for example. This paper gives an overview of the JHDL tool suite and presents a tutorial on JHDL syntax Date 1999 Proceedings Title Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on Conference Name Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on Volume 1 Pages 554-558 vol.1 DOI 10.1109/ACSSC.1999.832391 URL 10.1109/ACSSC.1999.832391 Accessed Saturday, September 25, 2010 2:56:57 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 2:56:57 PM Modified Saturday, September 25, 2010 2:56:57 PM Tags:
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Dynamic reconfiguration for management of radiation-induced faults in FPGAs
Type Document Author Paul Graham Maya Gokhale Abstract This paper describes novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex V1000 FPGAs to manage Single-Event Upset (SEU) faults owing to radiation in space environments. The on-orbit fault detection scheme uses radiation-hardened reconfiguration controllers to continuously monitor the configuration bitstreams of nine Virtex FPGAs and to correct errors by partial, dynamic reconfiguration of the FPGAs while they continue to execute. To study the SEU impact on our signal processing applications, we use a novel fault injection technique to corrupt configuration bits, thereby simulating SEU faults. By using dynamic reconfiguration, we can run the corrupted designs directly on the FPGA hardware, giving many orders of magnitude speed-up over purely software techniques. The fault injection method has been validated against proton beam testing, showing 97.6% agreement. Our work highlights the benefits of dynamic reconfiguration for space-based reconfigurable computing. Publisher Inderscience Publishers Date July 05, 2006 URL http://www.inderscience.com/link.php?
id=10162Accessed Saturday, September 25, 2010 3:46:23 PM Library Catalog ScientificCommons Date Added Saturday, September 25, 2010 3:46:23 PM Modified Saturday, September 25, 2010 3:46:23 PM Tags:
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Inderscience Publishers [http://www.inderscience.com/oai/oai2.php] (United Kingdom) ER
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Dynamic reconfiguration for management of radiation-induced faults in FPGAs
Type Conference Paper Author M. Gokhale Author P. Graham Author E. Johnson Author N. Rollins Author M. Wirthlin Abstract Summary form only given. We describe novel methods of exploiting the partial, dynamic reconfiguration capabilities of Xilinx Virtex 1000 FPGAs to manage transient faults due to radiation in space environments. The on-orbit fault detection scheme uses a radiation-hardened reconfiguration controller to continuously monitor the configuration bit streams of 9 Virtex FPGAs and to correct errors by partial, dynamic reconfiguration of the FPGAs while they continue to execute. To study single event upset (SEU) impact on our signal processing applications, we use a novel fault injection technique to corrupt configuration bits, thereby simulating SEU faults. By using dynamic reconfiguration, we can run the corrupted designs directly on the FPGA hardware, giving many orders of magnitude speed-up over purely software techniques. The fault injection method has been validated against proton beam testing, showing 97.6% agreement. Our work highlights the benefits of dynamic reconfiguration for space-based reconfigurable computing. Date 2004 Proceedings Title Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International Conference Name Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International Pages 145 DOI 10.1109/IPDPS.2004.1303127 URL 10.1109/IPDPS.2004.1303127 Accessed Saturday, September 25, 2010 3:46:02 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:46:02 PM Modified Saturday, September 25, 2010 3:46:02 PM Tags:
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Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
Type Conference Paper Author Michael J. Wirthlin Author Brian McMurtrey Abstract Constant coefficient multiplication using look-up tables is a popular form of multiplication in FPGAs. The ample look-up table resources found within the FPGA match well to the architecture of a look-up table based multiplier. While this form of multiplication maps well to FPGAs, it isn't particularly efficient. This paper presents an efficient variant of this multiplier using the advanced features of the Xilinx Virtex FPGA. Specifically, this approach combines the look-up and add operations required by this multiplier architecture. Date 2001 Proceedings Title Proceedings of the 11th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 555-564 ISBN 3-540-42499-7 URL http://portal.acm.org/citation.cfm?
id=647928.739905Accessed Saturday, September 25, 2010 3:57:58 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:57:58 PM Modified Saturday, September 25, 2010 3:57:58 PM Attachments
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Error control coding in software radios: an FPGA approach
Type Journal Article Author G.C. Ahlquist Author M. Rice Author B. Nelson Abstract Among the various tasks performed by software radios is the reconfiguration of the error control coding algorithm to match the requirement of the radio personality. In the digital radio processor, proper assignment of tasks between DSPs and FPGAs provides performance improvements over the use of DSPs alone. Error control coding functions are good candidates to reside on the FPGA side of this functional partition. Unfortunately, good VLSI designs for codes using BCH or Reed-Solomon codes do not map well to FPGAs. Good FPGA designs must parallelize at every opportunity, minimize timing delays through intelligent floor planning, and use each logic block to its fullest. We demonstrate the merits of these concepts by comparing the performance of popular finite field multiplier designs Publication Personal Communications, IEEE Volume 6 Issue 4 Pages 35-39 Date 1999 Journal Abbr Personal Communications, IEEE DOI 10.1109/98.788213 ISSN 1070-9916 Short Title Error control coding in software radios URL 10.1109/98.788213 Accessed Saturday, September 25, 2010 3:38:37 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:38:37 PM Modified Saturday, September 25, 2010 3:38:37 PM Tags:
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Fault Tolerant ICAP Controller for High-Reliable Internal Scrubbing
Type Conference Paper Author J. Heiner Author N. Collins Author M. Wirthlin Abstract High reliable reconfigurable applications today require system platforms that can easily and quickly detect and correct single event upsets. This capability, however, can be costly for FPGAs. This paper demonstrates a technique for detecting and repairing SEUs within the configuration memory of a Xilinx Virtex-4 FPGA using the ICAP interface. The internal configuration access port (ICAP) provides a port internal to the FPGA for configuring the FPGA device. An application note demonstrates how this port can be used for both error injection and scrubbing (L. Jones, 2007). We have extended this work to create a fault tolerant ICAP scrubber by triplicating the internal ICAP circuit using TMR and block memory scrubbing. This paper will describe the costs, benefits, and reliability of this fault-tolerant ICAP controller. Date 2008 Proceedings Title Aerospace Conference, 2008 IEEE Conference Name Aerospace Conference, 2008 IEEE Pages 1-10 DOI 10.1109/AERO.2008.4526471 ISBN 1095-323X URL 10.1109/AERO.2008.4526471 Accessed Saturday, September 25, 2010 3:54:03 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:54:03 PM Modified Saturday, September 25, 2010 3:54:03 PM Tags:
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Fine-Grain SEU Mitigation for FPGAs Using Partial TMR
Type Journal Article Author B. Pratt Author M. Caffrey Author J.F. Carroll Author P. Graham Author K. Morgan Author M. Wirthlin Abstract The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost. Publication Nuclear Science, IEEE Transactions on Volume 55 Issue 4 Pages 2274-2280 Date 2008 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2008.2000852 ISSN 0018-9499 URL 10.1109/TNS.2008.2000852 Accessed Saturday, September 25, 2010 3:15:24 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:15:24 PM Modified Saturday, September 25, 2010 3:15:24 PM Tags:
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FPGA partial reconfiguration via configuration scrubbing
Type Conference Paper Author J. Heiner Author B. Sellers Author M. Wirthlin Author J. Kalb Abstract SRAM-based FPGA devices are susceptible to single event effects (SEE) including single event upsets (SEU) within the configuration memory. Configuration scrubbing along with TMR or other hardware redundancy techniques are often used to mitigate the effects of these SEUs. However, the use of traditional configuration scrubbing prevents the ability to reconfigure the FPGA dynamically or to perform partial reconfiguration. This paper presents a novel technique that allows partial reconfiguration to be used with configuration scrubbing. A self scrubber, utilizing a small portion of the FPGA, performs the necessary operations to reconfigure a portion of the design while continuously scrubbing the entire FPGA. Date 2009 Proceedings Title Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Conference Name Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Pages 99-104 DOI 10.1109/FPL.2009.5272543 ISBN 1946-1488 URL 10.1109/FPL.2009.5272543 Accessed Saturday, September 25, 2010 3:51:21 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:51:21 PM Modified Saturday, September 25, 2010 3:51:21 PM Tags:
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FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing
Type Journal Article Author W. Sun Author M. J. Wirthlin Author S. Neuendorffer Abstract The primary goal during synthesis of digital signal processing (DSP) circuits is to minimize the hardware area while meeting a minimum throughput constraint. In field-programmable gate array (FPGA) implementations, significant area savings can be achieved by using slower, more area-efficient circuit modules and/or by time-multiplexing faster, larger circuit modules. Unfortunately, manual exploration of this design space is impractical. In this paper, we introduce a design exploration methodology that identifies the lowest cost FPGA pipelined implementation of an untimed synchronous data-flow graph by combined module selection with resource sharing under the context of pipeline scheduling. These techniques are applied together to minimize the area cost of the FPGA implementation while meeting a user-specified minimum throughput constraint. Two different algorithms are introduced for exploring the large design space. We show that even for small DSP algorithms, combining these techniques can offer significant area savings relative to applying any of them alone Publication Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 26 Issue 2 Pages 254-265 Date 2007 Journal Abbr Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on DOI 10.1109/TCAD.2006.887923 ISSN 0278-0070 URL 10.1109/TCAD.2006.887923 Accessed Saturday, September 25, 2010 3:45:40 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:45:40 PM Modified Saturday, September 25, 2010 3:45:40 PM Tags:
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FPGA-based sonar processing
Type Conference Paper Author Paul Graham Author Brent Nelson Abstract This paper presents the application of time-delay sonar beamforming and discusses a multi-board FPGA system for performing several variations of this beamforming method in real-time for realistic sonar arrays. Additionally, we show that our proposed FPGA system has a six to twelve times performance advantage over an equivalent system created using currently available, high-performance DSPs designed for multiprocessing systems. This performance advantage is due to the simplicity of the core calculation, the limitations of the the DSP's address calculation hardware, and the ability to customize the I/O of the FPGA to the application. Date 1998 Proceedings Title Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays Place Monterey, California, United States Publisher ACM Pages 201-208 DOI 10.1145/275107.275140 ISBN 0-89791-978-5 URL http://portal.acm.org/citation.cfm?
id=275140Accessed Saturday, September 25, 2010 3:39:02 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:39:02 PM Modified Saturday, September 25, 2010 3:39:02 PM Attachments
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Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows
Type Report Author Michael Wirthlin Author Brent Nelson Author Brad Hutchings Author Peter Athanas Author Shawn Bohner Abstract Interest is growing in the use of FPGA devices for high-performance, efficient parallel computation. The large amount of programmable logic, internal routing, and memory can be used to perform a wide variety of high-performance computation more efficiently than traditional microprocessor-based computing architectures. The productivity of FPGA design, however, is very low. FPGA design is very time consuming and requires low-level hardware design skills. This study investigated this FPGA design productivity problem and identified potential solutions that will provide revolutionary improvements in design productivity. Three research areas that must be addressed to achieve such improvements are significant improvement in reuse of FPGA circuits, identification and deployment of higher level design abstractions, and increasing the number of turns per day to significantly increase the number of design iterations. The results of this study suggest that with adequate advancement in each of these areas, FPGA design productivity can be increased by 25X over current practice. Date 2008-07 URL http://stinet.dtic.mil/oai/oai?
&verb=getRecord&…Accessed Saturday, September 25, 2010 3:08:10 PM Library Catalog Defense Technical Information Center Date Added Saturday, September 25, 2010 3:08:10 PM Modified Saturday, September 25, 2010 3:08:10 PM Tags:
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Genetic algorithms in software and in hardware-a performance analysis of workstation and custom computing machine implementations
Type Conference Paper Author P. Graham Author B. Nelson Abstract The paper analyzes the performance differences found between the hardware and software versions of a genetic algorithm used to solve the travelling salesman problem. The hardware implementation requires 4 FPGA's on a Splash 2 board and runs at 11 MHz. The software implementation was written in C++ and executed on a 125 MHz HP PA-RISC workstation. The software run time was more than four times that of the hardware (up to 50 times as many cycles). The paper analyses the contribution made to this performance difference by the following hardware features: hard-wired control, custom address generation logic, memory hierarchy efficiency, and both fine- and course-grained parallelism. The results indicate that the major contributor to the hardware performance advantage is fine-grained parallelism-RTL-level parallelism due to operator pipelining. This alone accounts for as much as a 38X cycle-count reduction over the software in one section of the algorithm. The next major contributors include hard-wired control and custom address generation which account for as much as a 3X speedup in other sections of the algorithm. Finally, memory hierarchy inefficiencies in the software (cache misses and paging) and coarse-grained parallelism in the hardware are each shown to have lesser effect on the performance difference between the implementations Date 1996 Proceedings Title FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on Conference Name FPGAs for Custom Computing Machines, 1996. Proceedings. IEEE Symposium on Pages 216-225 DOI 10.1109/FPGA.1996.564847 URL 10.1109/FPGA.1996.564847 Accessed Saturday, September 25, 2010 3:39:48 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:39:48 PM Modified Saturday, September 25, 2010 3:39:48 PM Tags:
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GigaOp DSP on FPGA: Special Issue on Field Programmable Logic
Type Web Page Author Hutchings B. L Author Nelson B. E Website Type Text Date May 2001 Short Title GigaOp DSP on FPGA URL http://www.ingentaconnect.com/content/klu/vlsi/2004/00000036/00000001/05149953 Accessed Saturday, September 25, 2010 2:48:10 PM Date Added Saturday, September 25, 2010 2:48:10 PM Modified Saturday, September 25, 2010 3:02:01 PM Tags:
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Higher Radix Floating-Point Representations for FPGA-Based Arithmetic
Type Conference Paper Author Bryan Catanzaro Author Brent Nelson Abstract FPGA implementations of floating-point operators have historically been designed to use binary floating-point representations. The general computing world settled on binary floating-point representations over three decades ago, and more recently, the FPGA community followed their example. Binary representations were chosen to maximize numerical accuracy per bit of data, however, the unique nature of FPGA-based computation makes numerical accuracy per unit of FPGA resources a more important measure of the usefulness of a given floating-point representation. In this paper, we show that higher radix floating-point representations are well suited to FPGA-based computations, especially high precision calculations which require the support of denormalized numbers. Higher radix representations use FPGA resources more efficiently. For example, a hexadecimal floating-point adder has a 30% smaller area-time product than its binary counterpart, while still delivering equal worst-case and better average-case numerical accuracy. Contrary to established belief, higher radix representations are useful for FPGA applications requiring IEEE 754 compliance, since they can deliver superior numerical performance while still using less FPGA resources. Date 2005 Proceedings Title Field-Programmable Custom Computing Machines, Annual IEEE Symposium on Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 161-170 DOI http://doi.ieeecomputersociety.org/10.1109/FCCM.2005.43 ISBN 0-7695-2445-1 Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 3:25:39 PM Modified Saturday, September 25, 2010 3:25:39 PM Notes:
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Improving FPGA Design Robustness with Partial TMR
Type Conference Paper Author B. Pratt Author M. Caffrey Author P. Graham Author K. Morgan Author M. Wirthlin Abstract This paper describes an efficient approach of applying mitigation to an FPGA design to protect against single event upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on their importance within the design. Higher priority is given to structures causing "persistent" errors within the design. For certain applications, applying selective mitigation to the persistent components can yield higher returns in reliability per unit cost than full mitigation. A software tool is also introduced which automatically classifies circuit structures based on this concept and applies triple modular redundancy (TMR) selectively based on the classification of the circuit structure Date 2006 Proceedings Title Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International Conference Name Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International Pages 226-232 DOI 10.1109/RELPHY.2006.251221 URL 10.1109/RELPHY.2006.251221 Accessed Saturday, September 25, 2010 3:14:54 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:14:54 PM Modified Saturday, September 25, 2010 3:14:54 PM Tags:
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Improving functional density through run-time constant propagation
Type Conference Paper Author Michael J. Wirthlin Author Brad L. Hutchings Abstract Circuit specialization techniques such as constant propagation are commonly used to reduce both the hardware resources and cycle time of digital circuits. When reconfigurable FPGAs are used, these advantages can be extended by dynamically specializing circuits using run-time reconfiguration (RTR). For systems exploiting constant propagation, hardware resources can be reduced by folding constants within the circuit and dynamically changing the constants using circuit reconfiguration. To measure the benefits of circuit specialization, a functional density metric is presented. This metric allows the analysis of both static and run-time reconfigured circuits by including the cost of circuit reconfiguration. This metric will be used to justify runtime constant propagation as well as analyze the effects of reconfiguration time on run-time reconfigured systems. Date 1997 Proceedings Title Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays Place Monterey, California, United States Publisher ACM Pages 86-92 DOI 10.1145/258305.258316 ISBN 0-89791-801-0 URL http://portal.acm.org/citation.cfm?
id=258305.258316Accessed Saturday, September 25, 2010 3:59:48 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:59:48 PM Modified Saturday, September 25, 2010 3:59:48 PM Attachments
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Improving functional density using run-time circuit reconfiguration [FPGAs]
Type Journal Article Author M.J. Wirthlin Author B.L. Hutchings Abstract The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach Publication Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 6 Issue 2 Pages 247-256 Date 1998 Journal Abbr Very Large Scale Integration (VLSI) Systems, IEEE Transactions on DOI 10.1109/92.678880 ISSN 1063-8210 URL 10.1109/92.678880 Accessed Saturday, September 25, 2010 3:49:09 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:49:09 PM Modified Saturday, September 25, 2010 3:49:09 PM Tags:
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Improving the FPGA Design Process through Determining and Applying Logical-to-Physical Design Mappings
Type Conference Paper Author P. Graham Author B. Hutchings Author B. Nelson Date 2000 Proceedings Title Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines Publisher IEEE Computer Society Pages 305 ISBN 0-7695-0871-5 URL http://portal.acm.org/citation.cfm?
id=795884Accessed Saturday, September 25, 2010 2:48:36 PM Library Catalog ACM Date Added Saturday, September 25, 2010 2:48:36 PM Modified Saturday, September 25, 2010 2:48:36 PM Attachments
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Improving the performance and efficiency of an adaptive amplification operation using configurable hardware
Type Conference Paper Author M.J. Wirthlin Author S. Morrison Author P. Graham Author B. Bray Abstract An adaptive amplification operation has been designed and tested in configurable hardware for a computationally intensive object recognition system. This configurable system provides over forty-one times the throughput of an industry-standard embedded processor by exploiting the bandwidth of internal block memories and parallelism within the algorithm. Operating at less than one half the power of the programmable processor, the configurable approach performs the computation with 90 times less energy. The improvements in both performance and power are obtained by customizing the datapath, memory interfaces, and control to the amplification algorithm Date 2000 Proceedings Title Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on Conference Name Field-Programmable Custom Computing Machines, 2000 IEEE Symposium on Pages 267-275 DOI 10.1109/FPGA.2000.903414 URL 10.1109/FPGA.2000.903414 Accessed Saturday, September 25, 2010 3:59:20 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:59:20 PM Modified Saturday, September 25, 2010 3:59:20 PM Tags:
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Incomplete Trace Data And Trace Driven Simulation
Type Journal Article Author J. Kelly Flanagan Author Brent E Nelson Author James K Archibald Author Knut Grimsrud Publication PROC. OF INTERNATIONAL WORKSHOP ON MODELING, ANALYSIS, AND SIMULATION OF COMPUTER AND TELECOMMUNICATION SYSTEMS Pages 203--209 Date 1995 URL http://citeseerx.ist.psu.edu/viewdoc/summary?
doi=10.1.1.5.3076Accessed Saturday, September 25, 2010 3:41:18 PM Date Added Saturday, September 25, 2010 3:41:18 PM Modified Saturday, September 25, 2010 3:41:18 PM -
Instrumenting Bitstreams for Debugging FPGA Circuits
Type Conference Paper Author Paul Graham Author Brent Nelson Author Brad Hutchings Abstract Since FPGAs are frequently used to improve the time to market for products, shortening the time for validating and debugging FPGA designs is, thus, important. Our paper discusses how directly instrumenting FPGA programming data, or bitstreams, with debugging hardware can improve the debugging productivity for designers and, thus, reduce a design?s time to market. We also provide some background relating to the current state of the art in debugging FPGA designs and describe how bitstream instrumentation can be automated using JHDL, JBits and JRoute. When instrumenting designs with embedded logic analyzers at the bitstream level, we have witnessed design modification speed-ups ranging from about 6 to 19 times over more conventional techniques. We will also briefly mention other applications of bitstream modification in debugging FPGA designs. Date 2001 Proceedings Title Field-Programmable Custom Computing Machines, Annual IEEE Symposium on Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 41-50 DOI http://doi.ieeecomputersociety.org/10.1109/FCCM.2001.26 ISBN 0-7695-2667-5 Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 2:46:03 PM Modified Saturday, September 25, 2010 2:46:03 PM Notes:
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IP delivery for FPGAs using Applets and JHDL
Type Conference Paper Author Michael J. Wirthlin Author Brian McMurtrey Abstract This paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor. Date 2002 Proceedings Title Proceedings of the 39th annual Design Automation Conference Place New Orleans, Louisiana, USA Publisher ACM Pages 2-7 DOI 10.1145/513918.513922 ISBN 1-58113-461-4 URL http://portal.acm.org/citation.cfm?
id=513922Accessed Saturday, September 25, 2010 3:56:44 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:56:44 PM Modified Saturday, September 25, 2010 3:56:44 PM Tags:
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JHDLBits: the merging of two worlds
Type Journal Article Author Ra Poetter Author Jesse Hunter Author Cameron Patterson Author Peter Athanas Author Brent Nelson Author Neil Steiner Publication 14TH INTERNATIONAL WORKSHOP ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS, FPL 2004 Date 2004 Short Title JHDLBits URL http://citeseerx.ist.psu.edu/viewdoc/summary?
doi=10.1.1.77.6533Accessed Saturday, September 25, 2010 3:27:00 PM Date Added Saturday, September 25, 2010 3:27:00 PM Modified Saturday, September 25, 2010 3:27:00 PM -
Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
Type Conference Paper Author Wesley J. Landaker Author Michael J. Wirthlin Author Brad Hutchings Date 2002 Proceedings Title Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 806-815 ISBN 3-540-44108-5 URL http://portal.acm.org/citation.cfm?
id=740236Accessed Saturday, September 25, 2010 3:56:28 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:56:28 PM Modified Saturday, September 25, 2010 3:56:28 PM Attachments
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Multitasking Hardware on the SLAAC1-V Reconfigurable Computing System
Type Conference Paper Author Wesley J. Landaker Author Michael J. Wirthlin Author Brad Hutchings Date 2002 Proceedings Title Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 806-815 ISBN 3-540-44108-5 URL http://portal.acm.org/citation.cfm?
id=740236Accessed Saturday, September 25, 2010 3:04:01 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:04:01 PM Modified Saturday, September 25, 2010 3:04:01 PM Attachments
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Noise impact of single-event upsets on an FPGA-based digital filter
Type Conference Paper Author B.H. Pratt Author M.J. Wirthlin Author M. Caffrey Author P. Graham Author K. Morgan Abstract Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output. Date 2009 Proceedings Title Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Conference Name Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on Pages 38-43 DOI 10.1109/FPL.2009.5272554 ISBN 1946-1488 URL 10.1109/FPL.2009.5272554 Accessed Saturday, September 25, 2010 3:16:35 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:16:35 PM Modified Saturday, September 25, 2010 3:16:35 PM Tags:
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Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture
Type Conference Paper Author Eric Roesler Author Brent E. Nelson Date 2002 Proceedings Title Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 637-646 ISBN 3-540-44108-5 URL http://portal.acm.org/citation.cfm?
id=740071Accessed Saturday, September 25, 2010 3:33:12 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:33:12 PM Modified Saturday, September 25, 2010 3:33:12 PM Attachments
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On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat)
Type Conference Paper Author M. Caffrey Author K. Morgan Author D. Roussel-Dupre Author S. Robinson Author A. Nelson Author A. Salazar Author M. Wirthlin Author W. Howes Author D. Richins Abstract The Cibola Flight Experiment (CFE) is an experimental small satellite developed at the Los Alamos National Laboratory to demonstrate the feasibility of using FPGA-based reconfigurable computing for sensor processing in a space environment. The CFE satellite was launched on March 8, 2007 in low-earth orbit and has operated extremely well since its deployment. The nine Xilinx Virtex FPGAs used in the payload have been used for several high-throughput sensor processing applications and for single-event upset (SEU) monitoring and mitigation. This paper will describe the CFE system and summarize its operational results. In addition, this paper will describe the results from several SEU detection circuits that were performed on the spacecraft. Date 2009 Proceedings Title Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on Conference Name Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on Pages 3-10 DOI 10.1109/FCCM.2009.22 URL 10.1109/FCCM.2009.22 Accessed Saturday, September 25, 2010 3:52:35 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:52:35 PM Modified Saturday, September 25, 2010 3:52:35 PM Tags:
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OpenFPGA CoreLib core library interoperability effort
Type Journal Article Author M. Wirthlin Author D. Poznanovic Author P. Sundararajan Author A. Coppola Author D. Pellerin Author W. Najjar Author R. Bruce Author M. Babst Author O. Pritchard Author P. Palazzari Author G. Kuzmanov Abstract This paper begins by summarizing the goals of the OpenFPGA CoreLib Working Group to facilitate the interoperability of FPGA circuit cores within a variety of FPGA design tools, including high-level programming tools targeting FPGA architectures. This effort is contrasted with other IP reuse efforts. The paper reviews the current approach used by several high-level language compilers to integrate IP within their tool. The CoreLib approach for standardizing this IP integration is proposed followed by an example that demonstrates its utility. Finally, the current state of the effort and future plans are presented. Publication Parallel Computing Volume 34 Issue 4-5 Pages 231-244 Date May 2008 DOI 10.1016/j.parco.2008.03.004 ISSN 0167-8191 URL http://www.sciencedirect.com/science/article/B6V12-4S5FJ75-1/2/dfcc919b1a773a3176b763eb6cfba9c1 Accessed Saturday, September 25, 2010 3:45:09 PM Library Catalog ScienceDirect Date Added Saturday, September 25, 2010 3:45:09 PM Modified Saturday, September 25, 2010 3:45:09 PM Tags:
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Optical Flow on the Ambric Massively Parallel Processor Array (MPPA)
Type Conference Paper Author Brad Hutchings Author Brent Nelson Author Stephen West Author Reed Curtis Abstract The Ambric Massively Parallel Processor Array (MPPA) is a device that contains 336 32-bit RISC processors and is appropriate for embedded systems due to its relatively small physical and power footprint. Optical flow is a computationally-demanding and highly parallelizeable image-processing algorithm with applications in embedded systems such as robotics and autonomous vehicles. An optical flow algorithm is implemented on the Ambric device and is shown to achieve near FPGA performance at similar levels of power consumption while requiring many fewer lines of code (Java) than its FPGA counterpart (VHDL). Date 2009 Proceedings Title Field-Programmable Custom Computing Machines, Annual IEEE Symposium on Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 141-148 DOI http://doi.ieeecomputersociety.org/10.1109/FCCM.2009.21 ISBN 978-0-7695-3716-0 Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 2:58:59 PM Modified Saturday, September 25, 2010 2:58:59 PM Tags:
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Optimal Finite Field Multipliers for FPGAs
Type Conference Paper Author Gregory C. Ahlquist Author Brent E. Nelson Author Michael Rice Date 1999 Proceedings Title Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 51-60 ISBN 3-540-66457-2 URL http://portal.acm.org/citation.cfm?
id=739205Accessed Saturday, September 25, 2010 3:37:07 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:37:07 PM Modified Saturday, September 25, 2010 3:37:07 PM Attachments
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PNoC: a flexible circuit-switched NoC for FPGA-based systems
Type Journal Article Author C. Hilton Author B. Nelson Abstract Increases in chip density due to Moore's law allow for the implementation of ever larger and more complex systems on a single chip (SoCs). The communication mechanisms employed in such SoCs are an important contribution to their overall performance. Networks on chip (NoCs) promise to overcome the scalability problems found in bus-based interconnect. To date, most work has focused on packet-switched NoCs. Circuit-switched networks are an intriguing alternative, which promise high communication rates and predictable communication latencies. A new lightweight circuit-switched architecture called programmable NoC (PNoC) is described. PNoC is a flexible architecture that is suitable for use in FPGA-based systems. Implementation results on a Virtex-II Pro device are given using an image binarisation demonstration which resulted in as much as a 23× speedup compared with a shared bus implementation. Publication Computers and Digital Techniques, IEE Proceedings - Volume 153 Issue 3 Pages 181-188 Date 2006 Journal Abbr Computers and Digital Techniques, IEE Proceedings - DOI 10.1049/ip-cdt:20050175 ISSN 1350-2387 Short Title PNoC URL 10.1049/ip-cdt:20050175 Accessed Saturday, September 25, 2010 3:24:21 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:24:21 PM Modified Saturday, September 25, 2010 3:24:21 PM Tags:
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Real-Time Optical Flow Calculations on FPGA and GPU Architectures: A Comparison Study
Type Conference Paper Author J. Chase Author B. Nelson Author J. Bodily Author Zhaoyi Wei Author Dah-Jye Lee Abstract FPGA devices have often found use as higher-performance alternatives to programmable processors for implementing a variety of computations. Applications successfully implemented on FPGAs have typically contained high levels of parallelism and have often used simple statically-scheduled control and modest arithmetic. Recently introduced computing devices such as coarse grain reconfigurable arrays, multi-core processors, and graphical processing units (GPUs) promise to significantly change the computational landscape for the implementation of high-speed real-time computing tasks. One reason for this is that these architectures take advantage of many of the same application characteristics that fit well on FPGAs. One real-time computing task, optical flow, is difficult to apply in robotic vision applications in practice because of its high computational and data rate requirements, and so is a good candidate for implementation on FPGAs and other custom computing architectures. In this paper, a tensor-based optical flow algorithm is implemented on both an FPGA and a GPU and the two implementations discussed. The two implementations had similar performance, but with the FPGA implementation requiring 12Ã more development time. Other comparison data for these two technologies is then given for three additional applications taken from a MIMO digital communication system design, providing additional examples of the relative capabilities of these two technologies. Date 2008 Proceedings Title Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on Conference Name Field-Programmable Custom Computing Machines, 2008. FCCM '08. 16th International Symposium on Pages 173-182 DOI 10.1109/FCCM.2008.24 Short Title Real-Time Optical Flow Calculations on FPGA and GPU Architectures URL 10.1109/FCCM.2008.24 Accessed Saturday, September 25, 2010 3:21:49 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:21:49 PM Modified Saturday, September 25, 2010 3:21:49 PM Tags:
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Reconfigurable computing application frameworks
Type Conference Paper Author A.L. Slade Author B.E. Nelson Author B.L. Hutchings Abstract FPGA-based (field programmable gate array) configurable computing machines (CCMs) offer powerful and flexible general-purpose computing platforms. However, development for FPGA-based designs using modern CAD (computer aided design) tools is geared mainly toward an ASIC-like process. This is inadequate for the needs of CCM application development. This paper discusses an application framework for developing CCM-based applications beyond just the hardware configuration. This framework leverages the advantages of CCMs (availability, programmability, visibility, and controllability) to help create CCM-based applications throughout the entire development process (i.e. design, debug, and deploy). The framework itself is deployed with the final application, thus permitting dynamic circuit configurations that include data folding optimizations based on user input. The resulting system aids in creating applications that are potentially more intuitive, easier to develop, and better performing. An example application demonstrates the use of the application framework and the potential benefits. Date 2003 Proceedings Title Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on Conference Name Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on Pages 251-260 DOI 10.1109/FPGA.2003.1227260 ISBN 1082-3409 URL 10.1109/FPGA.2003.1227260 Accessed Saturday, September 25, 2010 2:47:38 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 2:47:38 PM Modified Saturday, September 25, 2010 2:47:38 PM Tags:
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Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing
Type Conference Paper Author Paul Graham Author Brent E. Nelson Date 1999 Proceedings Title Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 1-10 ISBN 3-540-66457-2 URL http://portal.acm.org/citation.cfm?
id=647926.739230Accessed Saturday, September 25, 2010 3:37:57 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:37:57 PM Modified Saturday, September 25, 2010 3:37:57 PM Attachments
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Reliable Communications Using FPGAs in High-Radiation Environments - Part I: Characterization
Type Conference Paper Author B. Pratt Author M. Fuller Author M. Rice Author M. Wirthlin Abstract Reconfigurable radios implemented on FPGAs operating in high-radiation environments are subject to single-event- upsets (SEUs). The traditional mitigation method of applying triple modular redundancy (TMR) to the entire design does not have to be used in this application. This is because the majority of the SEUs impact the overall performance (measured by bit error rate) in the same way additive noise does. The results of this paper show which sections must be protected from SEUs and provide a guide for the bit error rate performance versus FPGA area tradeoff as a function of SEU mitigation. Date 2010 Proceedings Title Communications (ICC), 2010 IEEE International Conference on Conference Name Communications (ICC), 2010 IEEE International Conference on Pages 1-5 DOI 10.1109/ICC.2010.5502571 ISBN 1550-3607 Short Title Reliable Communications Using FPGAs in High-Radiation Environments - Part I URL 10.1109/ICC.2010.5502571 Accessed Saturday, September 25, 2010 3:17:39 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:17:39 PM Modified Saturday, September 25, 2010 3:17:39 PM -
Senior-level embedded system design project using FPGAs
Type Conference Paper Author M.J. Wirthlin Abstract There is a growing need to provide students with meaningful system-level design (SLD) experiences at the undergraduate level. Relevant SLD skills include the ability to integrate IP from third-party providers, create reusable IP (including appropriate documentation), partition system functionality between software and hardware, and properly integrate real-time functions within an operating system. A senior SLD project was created to provide such an experience for undergraduate students. With cooperation from Xilinx corporation, this single semester course provides students the opportunity to learn SLD skills by creating a single-chip multimedia computer system using FPGAs. Students in this class integrate custom IP and third-party IP into a PowerPC-based system within a single FPGA device. The final product is a real-time multimedia computer system providing both audio and video services. This paper describes the SLD course, beginning by outlining its goals and requirements. Next, the hardware and software infrastructure used by the project is described. Finally, the class schedule is reviewed. Date 2005 Proceedings Title Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on Conference Name Microelectronic Systems Education, 2005. (MSE '05). Proceedings. 2005 IEEE International Conference on Pages 91-92 DOI 10.1109/MSE.2005.49 URL 10.1109/MSE.2005.49 Accessed Saturday, September 25, 2010 3:54:48 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:54:48 PM Modified Saturday, September 25, 2010 3:54:48 PM Tags:
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Sequencing Run-Time Reconfigured Hardware with Software
Type Conference Paper Author M.J. Wirthlin Author B.L. Hutchings Abstract Run-Time Reconfigured systems offer additional hardware resources to systems based on reconfigurable FPGAs. These systems, however, are often difficult to build and must tolerate substantial reconfiguration times. A processor based architecture has been built to simplify the development of these systems by providing programmable control of hardware sequencing while retaining the performance of hardware. Configuration overhead of this system is reduced by "caching" hardware on the reconfigurable resource. An image processing application was developed on this system to demonstrate both the performance improvements of custom hardware and the ease of software development. Date 1996 Proceedings Title Field-Programmable Gate Arrays, 1996. FPGA '96. Proceedings of the 1996 ACM Fourth International Symposium on Conference Name Field-Programmable Gate Arrays, 1996. FPGA '96. Proceedings of the 1996 ACM Fourth International Symposium on Pages 122-128 DOI 10.1109/FPGA.1996.242439 URL 10.1109/FPGA.1996.242439 Accessed Saturday, September 25, 2010 4:00:16 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 4:00:16 PM Modified Saturday, September 25, 2010 4:00:16 PM -
SEU mitigation for half-latches in Xilinx Virtex FPGAs
Type Journal Article Author P. Graham Author M. Caffrey Author D.E. Johnson Author N. Rollins Author M. Wirthlin Abstract The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field programmable gate arrays (FPGAs) make them very interesting for high-speed on-orbit data processing, but the current generation of radiation-tolerant SRAM-based FPGAs are based on commercial-off-the-shelf technologies and, consequently, are susceptible to single-event upset effects. In this paper, we discuss in detail the consequences of radiation-induced single-event upsets (SEUs) in the state of half-latch structures found in Xilinx Virtex FPGAs and describe methods for mitigating the effects of half-latch SEUs. One mitigation method's effectiveness is then illustrated through experimental data gathered through proton accelerator testing at Crocker Nuclear Laboratory, University of California-Davis. For the specific design and mitigation methodology tested, the mitigated design demonstrated more than an order of magnitude improvement in reliability over the unmitigated version of the design in regards to average proton fluence until circuit failure. Publication Nuclear Science, IEEE Transactions on Volume 50 Issue 6 Pages 2139-2146 Date 2003 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2003.820744 ISSN 0018-9499 URL 10.1109/TNS.2003.820744 Accessed Saturday, September 25, 2010 3:47:20 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:47:20 PM Modified Saturday, September 25, 2010 3:47:20 PM Tags:
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SEU-induced persistent error propagation in FPGAs
Type Journal Article Author K. Morgan Author M. Caffrey Author P. Graham Author E. Johnson Author B. Pratt Author M. Wirthlin Abstract This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the nonpersistent cross section causes a temporary interruption of service. These cross sections have been measured for several designs using fault-injection and proton testing. Some FPGA applications may realize increased reliability at lower costs by focusing SEU mitigation on just the persistent cross section. Publication Nuclear Science, IEEE Transactions on Volume 52 Issue 6 Pages 2438-2445 Date 2005 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2005.860674 ISSN 0018-9499 URL 10.1109/TNS.2005.860674 Accessed Saturday, September 25, 2010 3:13:17 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:13:17 PM Modified Saturday, September 25, 2010 3:13:17 PM Tags:
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SRAM FPGA Reliability Analysis for Harsh Radiation Environments
Type Journal Article Author P.S. Ostler Author M.P. Caffrey Author D.S. Gibelyou Author P.S. Graham Author K.S. Morgan Author B.H. Pratt Author H.M. Quinn Author M.J. Wirthlin Abstract This paper investigates the viability of deploying SRAM-based FPGAs into harsh Earth-orbit environments. A reliability model is presented for estimating the MTTF of SRAM FPGA designs in specific orbits and orbit conditions. The model requires orbit- and condition-specific SEU rates and design-specific estimates of the probability of failure during a single scrubbing period. Probability of failure estimates are reported for several FPGA designs from both fault-injection and accelerator experiments. The model also includes a method for estimating composite mean time to failure (MTTF) that incorporates all orbit conditions over a solar cycle. Despite using pessimistic assumptions, the results from this model suggest that SRAM FPGA designs protected by TMR and scrubbing operate very reliably in a LEO orbit and surprisingly well in ¿harsh¿ orbits. Publication Nuclear Science, IEEE Transactions on Volume 56 Issue 6 Pages 3519-3526 Date 2009 Journal Abbr Nuclear Science, IEEE Transactions on DOI 10.1109/TNS.2009.2033381 ISSN 0018-9499 URL 10.1109/TNS.2009.2033381 Accessed Saturday, September 25, 2010 3:43:44 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:43:44 PM Modified Saturday, September 25, 2010 3:43:44 PM Tags:
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Synthesizing RTL Hardware from Java Byte Codes
Type Conference Paper Author Michael J. Wirthlin Author Brad Hutchings Author Carl Worth Abstract Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references. Date 2001 Proceedings Title Proceedings of the 11th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 123-132 ISBN 3-540-42499-7 URL http://portal.acm.org/citation.cfm?
id=647928.760947Accessed Saturday, September 25, 2010 3:58:22 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:58:22 PM Modified Saturday, September 25, 2010 3:58:22 PM Attachments
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The Mythical CCM: In Search of Usable (and Resuable) FPGA-Based General Computing Machines
Type Conference Paper Author Brent E. Nelson Abstract Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine - the configurable computing machine (CCM). The earliest CCMs featured rudimentary but significant integrated design, debug, and runtime environments. This paper reviews those environments as well as more recent work using JHDL, designed to investigate how a symbolic hardware debugging environment for CCMs can be created with many of the features normally associated with software debug systems. The paper reviews lessons learned from that work and concludes by discussing the role integrated design, debug, and runtime environments may play in future CCM-based systems. Date 2006 Proceedings Title Application-Specific Systems, Architectures and Processors, IEEE International Conference on Place Los Alamitos, CA, USA Publisher IEEE Computer Society Volume 0 Pages 5-14 DOI http://doi.ieeecomputersociety.org/10.1109/ASAP.2006.65 Short Title The Mythical CCM Library Catalog IEEE Computer Society Date Added Saturday, September 25, 2010 3:04:29 PM Modified Saturday, September 25, 2010 3:04:29 PM Notes:
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The reliability of FPGA circuit designs in the presence of radiation induced configuration upsets
Type Conference Paper Author M. Wirthlin Author E. Johnson Author N. Rollins Author M. Caffrey Author P. Graham Abstract FPGAs are an appealing solution for space-based remote sensing applications. However, in a low-Earth orbit, FPGAs (field programmable gate arrays) are susceptible to Single-Event Upsets (SEUs). In an effort to understand the effects of SEUs, an SEU simulator based on the SLAAC-1V computing board has been developed. This simulator artificially upsets the configuration memory of an FPGA and measures its impact on FPGA designs. The accuracy of this simulation environment has been verified using ground-based radiation testing. This simulation tool is being used to characterize the reliability of SEU mitigation techniques for FPGAs. Date 2003 Proceedings Title Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on Conference Name Field-Programmable Custom Computing Machines, 2003. FCCM 2003. 11th Annual IEEE Symposium on Pages 133-142 DOI 10.1109/FPGA.2003.1227249 ISBN 1082-3409 URL 10.1109/FPGA.2003.1227249 Accessed Saturday, September 25, 2010 3:55:53 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:55:53 PM Modified Saturday, September 25, 2010 3:55:53 PM Tags:
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Tradeoffs of Designing Floating-Point Division and Square Root on Virtex FPGAs
Type Conference Paper Author Xiaojun Wang Author Brent E. Nelson Abstract Low latency, high throughput and small area arethree major design considerations of an FPGA design.In this paper, we present a high radix SRT divisionalgorithm and a binary restoring square root algorithm.We describe three implementations of floating-pointdivision operations with variable width and precisionbased on Virtex-2 FPGAs.One is a low costiterative implementation; another is a low latency arrayimplementation; and the third is a high throughputpipelined implementation.The implementationsof floating-point square root operations are presentedas well.In addition to presenting the design of thesemodules, we analyze the tradeoffs among cost, latencyand throughput with strategies on how to reduce thecost, or improve the performance. Date 2003 Proceedings Title Proceedings of the 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Publisher IEEE Computer Society Pages 195 ISBN 0-7695-1979-2 URL http://portal.acm.org/citation.cfm?
id=938383.938389Accessed Saturday, September 25, 2010 3:32:10 PM Library Catalog ACM Date Added Saturday, September 25, 2010 3:32:10 PM Modified Saturday, September 25, 2010 3:32:10 PM Attachments
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Unified Debug Environment for Adaptive Computing Systems
Type Report Author Brad Hutchings Author Brent Nelson Author Mike Wirthlin Author Doran Wilde Abstract Adaptive computing systems (ACS) are hardware systems based around FPGA technology. Historically, design and debug tools for such systems have been based on ASIC technology. However, FPGA technology provides features which suggest different approaches be used for debug. For example, readback is a feature available in many FPGA devices which provides the ability to query an executing FPGA device for its entire internal state, providing unprecedented visibility into the executing design. The central element of the debug environment developed in this work is a debug services module (DSM). It provides a unified simulation/hardware execution debug environment which allows the user to debug the executing hardware in the context of the original design environment. This means signal values in the executing hardware can be viewed and manipulated using their original signal names from the design source. In addition, the DSM provides the following support for designs running on ACS platforms: checkpointing, multitasking, remote access, and interfacing with external high-level design tools. Finally, the DSM provides support for the automatic synthesis of debug circuitry to enable rapid instrumentation of FPGA designs for debug purposes. This report summarizes the debug system and a number of the experiments completed using it. Date 2003-09 URL http://stinet.dtic.mil/oai/oai?
&verb=getRecord&…Accessed Saturday, September 25, 2010 3:07:11 PM Library Catalog Defense Technical Information Center Date Added Saturday, September 25, 2010 3:07:11 PM Modified Saturday, September 25, 2010 3:07:11 PM Tags:
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Unifying simulation and execution in a design environment for FPGA systems
Type Journal Article Author B.L. Hutchings Author B.E. Nelson Abstract Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: (1) availability of the hardware during design and debug; (2) programmability; and (3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10000× faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware Publication Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Volume 9 Issue 1 Pages 201-205 Date 2001 Journal Abbr Very Large Scale Integration (VLSI) Systems, IEEE Transactions on DOI 10.1109/92.920834 ISSN 1063-8210 URL 10.1109/92.920834 Accessed Saturday, September 25, 2010 3:35:04 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:35:04 PM Modified Saturday, September 25, 2010 3:35:04 PM Tags:
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Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification
Type Conference Paper Author Timothy Wheeler Author Paul Graham Author Brent E. Nelson Author Brad Hutchings Abstract This paper describes a structured technique for providing full observability and controllability for functionally debugging FPGA designs in hardware, capabilities which are currently not available otherwise. Similar in concept to flip-flop scan chains for VLSI, our design-level scan technique includes all FPGA flip-flops and RAMs in a serial scan chain using FPGA logic rather than transistor logic. This paper describes the general procedure for modifying designs with design-level scan chains and provides the results of adding scan to several designs, both large and small. We observed an average FPGA resource overhead of 84% for full scan and only 60% when we augmented existing FPGA capabilities with scan to provide complete observability and controllability in hardware. Date 2001 Proceedings Title Proceedings of the 11th International Conference on Field-Programmable Logic and Applications Publisher Springer-Verlag Pages 483-492 ISBN 3-540-42499-7 URL http://portal.acm.org/citation.cfm?
id=647928.739887Accessed Saturday, September 25, 2010 2:47:05 PM Library Catalog ACM Date Added Saturday, September 25, 2010 2:47:05 PM Modified Saturday, September 25, 2010 2:47:05 PM Attachments
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Using Duplication with Compare for On-line Error Detection in FPGA-based Designs
Type Conference Paper Author J. Johnson Author W. Howes Author M. Wirthlin Author D.L. McMurtrey Author M. Caffrey Author P. Graham Author K. Morgan Abstract It is well known that SRAM-based FPGAs are susceptible to single-event upsets (SEUs) in radiation environments. A variety of mitigation strategies have been demonstrated to provide appropriate mitigation and correction of SEUs in these environments. While full mitigation of SEUs is appropriate for some situations, some systems may tolerate SEUs as long as these upsets are detected quickly and correctly. These systems require effective error detection techniques rather than costly error correction methods. This work leverages a well-known error detection technique for FPGAs called duplication with compare (DWC). This technique has been shown to be very effective at quickly and accurately detecting SEUs using fault injection and radiation testing. Date 2008 Proceedings Title Aerospace Conference, 2008 IEEE Conference Name Aerospace Conference, 2008 IEEE Pages 1-11 DOI 10.1109/AERO.2008.4526470 ISBN 1095-323X URL 10.1109/AERO.2008.4526470 Accessed Saturday, September 25, 2010 3:53:45 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:53:45 PM Modified Saturday, September 25, 2010 3:53:45 PM Tags:
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Using general-purpose programming languages for FPGA design
Type Conference Paper Author Brad L. Hutchings Author Brent E. Nelson Abstract General-purpose programming languages (GPL) are effective vehicles for FPGA design because they are easy to use, extensible, widely available, and can be used to describe both the hardware and software aspects of a design. The strengths of the GPL approach to circuit design have been demonstrated by JHDL, a Java-based circuit design environment used to develop several large FPGA-based applications at several institutions. Major strengths of the JHDL environment include a common run-time for both simulation and hardware execution, and the overall extensibility of the parent Java environment. The common run-time environment means that all validation and support software (testbenches, application-specific interfaces, graphical user interfaces, etc.) can be used without modification with the built-in simulator or with the executing application as it runs in hardware. Extensibility also plays a big role because designers can easily add new capability to the environment by writing additional tools in the parent language, Java, using the wide variety of available libraries. This paper gives a brief introduction to JHDL syntax and demonstrates its features with an end-to-end application example. Date 2000 Proceedings Title Proceedings of the 37th Annual Design Automation Conference Place Los Angeles, California, United States Publisher ACM Pages 561-566 DOI 10.1145/337292.337581 ISBN 1-58113-187-9 URL http://portal.acm.org/citation.cfm?
id=337292.337581Accessed Saturday, September 25, 2010 2:45:50 PM Library Catalog ACM Date Added Saturday, September 25, 2010 2:45:50 PM Modified Saturday, September 25, 2010 2:45:50 PM Attachments
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Web-based IP evaluation and distribution using applets
Type Journal Article Author M.J. Wirthlin Author B. McMurtrey Abstract This paper introduces an IP evaluation and delivery framework that operates within Java applets. The use of such applets allows circuit designers to create, evaluate, test, and obtain FPGA circuits directly within a Web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. An important component of this framework is the ability to deliver black-box simulation models as executable Java applets. These applet-based simulation models can be tied to third-party simulation tools using network sockets. Several techniques for interfacing black-box applet models to external simulators are described. Publication Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 22 Issue 8 Pages 985-994 Date 2003 Journal Abbr Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on DOI 10.1109/TCAD.2003.814946 ISSN 0278-0070 URL 10.1109/TCAD.2003.814946 Accessed Saturday, September 25, 2010 3:48:12 PM Library Catalog IEEE Xplore Date Added Saturday, September 25, 2010 3:48:12 PM Modified Saturday, September 25, 2010 3:48:12 PM Tags:
Brigham Young University - Provo | Fulton College of Engineering and Technology | The Church of Jesus Christ of Latter-day Saints
Configurable Computing Lab - Department of Electrical and Computer Engineering, CB 461, BYU, Provo, UT 84602 - (801)422-7206 - Copyright 2010. All Rights Reserved
Configurable Computing Lab - Department of Electrical and Computer Engineering, CB 461, BYU, Provo, UT 84602 - (801)422-7206 - Copyright 2010. All Rights Reserved