A Method and Case Study on Identifying Physically Adjacent Multiple-Cell Upsets Using 28-nm, Interleaved and SECDED-Protected Arrays

Author M. Wirthlin; D. Lee; G. Swift; H. Quinn
Abstract Extracting information about MCUs from SEU data sets can be a challenge without physical layout information. Many modern static-random access memory (SRAM) components interleave memory cells to improve the robustness of error-correcting codes (ECC) that detect and correct errors in the memory array. Bit interleaving has also become popular with other components with large SRAM arrays, including field-programmable gate arrays (FPGAs). In this paper, we present a technique for extracting MCUs statistically from radiation test data. Further, we use this technique to extract MCU information from a 28-nm FPGA that uses interleaving to protect the configuration memory.
Publication IEEE Transactions on Nuclear Science
Volume 61
Issue 6
Pages 3080-3087
Date 2014
DOI 10.1109/TNS.2014.2366913
ISSN 0018-9499;00189499


Arrays;Error correction codes;Field programmable gate arrays;Layout;SRAM cells