The BYU Configurable Computing Lab is home to a variety of software and hardware platforms:

  • The JHDL system is a CAD tool suite used for FPGA design and debug. It is available via open-source athttp://www.jhdl.org/. It has also been utilized in the BYU FPGA reliability work.
  • The BYU EDIF tool suite provides an API for creating, modifying, or analyzing EDIF netlists within the Java programming language. We are currently using this API to analyze EDIF netlists as a part of our FPGA reliability project. We intend to keep the API as general as possible to support other netlist analysis and manipulation activities. It is freely available for download here.
  • The BYU Reliability Tool Suite has been released in an open-source form for use by others in the community. See the BYU EDIF Tools homepage for more information.
  • The lab houses a wide variety of high-performance embedded platforms from Xilinx, Nallatech, and Rincon Research Corporation. For example:
    • Xilinx Virtex II Pro-based board from SEAKR Engineering with Virtex 4 SX55 daughter card. Same platform utilized by the Xilinx Radiation Test Consortium (XRTC).
    • Multiple Xilinx Virtex 4 prototype boards (ML40x, etc.) with which self-scrubbing capabilities utilizing the internal configuration access port (ICAP) have been demonstrated and investigated.
    • Several advanced GPU boards used for GP-GPU research.
    • SLAAC-1V PCI board with three Virtex 1000 FPGAs. Platform for the BYU-LANL fault injection tool.
    • DSPBrik FPGA DSP board from Rincon Research Corporation.
    • More specialized hardware to come…
  • Extensive commercial CAD tool suites from Xilinx, Nallatech, Cadence, Mentor, Synplicity, National Instruments, Impulse, Cebatech, and Celoxica are also available to support the laboratory’s work.
  • The laboratory also has access to the Fulton Supercomputing Laboratory consisting of six different supercomputers with more than 1,750 processing nodes total.